ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, SLIP 2017, Austin, TX, USA, June 17, 2017 - researchr publication

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ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, SLIP 2017, Austin, TX, USA, June 17, 2017. IEEE, 2017. [doi]

Conference: slip2017

Abstract is missing.

Fence-aware detailed-routability driven placementWing-Kai Chow, Jian Kuang 0001, Peishan Tu, Evangeline F. Y. Young. 1-7 [doi]

Timing driven routing tree constructionPeishan Tu, Wing-Kai Chow, Evangeline F. Y. Young. 1-8 [doi]

Clock tree synthesis for heterogeneous 3-D integrated circuitsIsuru Daulagala, Ioannis Savidis. 1-6 [doi]

Reconfigurable topology synthesis for application-specific noc on partially dynamically reconfigurable FPGAsJinglei Huang, Xiaodong Xu, Lan Yao, Song Chen. 1-8 [doi]

Analyzing voltage bias and temperature induced aging effects in photonic interconnects for manycore computingSai Vineel Reddy Chittamuru, Ishan G. Thakkar, Sudeep Pasricha. 1-8 [doi]

Slew-down: analysis of slew relaxation for low-impact clock buffersScott Lerner, Eric Leggett, Baris Taskin. 1-4 [doi]

A charge recovery logic system busLeo Filippini, Baris Taskin. 1-4 [doi]

Frontiers of timingUlf Schlichtmann. 1-4 [doi]

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