A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor

John Davis, Don Plass, Paul Bunce, Yuen H. Chan, Antonio Pelella, Rajiv V. Joshi, A. Chen, William V. Huott, Thomas J. Knips, Pradip Patel, K. Lo, Eric Fluhr. A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor. In 2006 IEEE International Solid State Circuits Conference, ISSCC 2006, Digest of Technical Papers, an Francisco, CA, USA, February 6-9, 2006. pages 2564-2571, IEEE, 2006. [doi]

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