Partha De, Chittaranjan Mandal 0002, Udaya Prampalli. Path-Balanced Logic Design to Realize Block Ciphers Resistant to Power and Timing Attacks. IEEE Trans. VLSI Syst., 27(5):1080-1092, 2019. [doi]
@article{DeMP19,
title = {Path-Balanced Logic Design to Realize Block Ciphers Resistant to Power and Timing Attacks},
author = {Partha De and Chittaranjan Mandal 0002 and Udaya Prampalli},
year = {2019},
doi = {10.1109/TVLSI.2019.2896377},
url = {https://doi.org/10.1109/TVLSI.2019.2896377},
researchr = {https://researchr.org/publication/DeMP19},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {27},
number = {5},
pages = {1080-1092},
}