Path-Balanced Logic Design to Realize Block Ciphers Resistant to Power and Timing Attacks

Partha De, Chittaranjan Mandal 0002, Udaya Prampalli. Path-Balanced Logic Design to Realize Block Ciphers Resistant to Power and Timing Attacks. IEEE Trans. VLSI Syst., 27(5):1080-1092, 2019. [doi]

Abstract

Abstract is missing.