Racetrack memory-based encoder/decoder for low-power interconnect architectures

Suman Deb, Leibin Ni, Hao Yu, Anupam Chattopadhyay. Racetrack memory-based encoder/decoder for low-power interconnect architectures. In Walid A. Najjar, Andreas Gerstlauer, editors, International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2016, Agios Konstantinos, Samos Island, Greece, July 17-21, 2016. pages 281-287, IEEE, 2016. [doi]

Abstract

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