A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation - researchr publication authors

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Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa. A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation. In 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014, Singapore, January 20-23, 2014. pages 21-22, IEEE, 2014. [doi]

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