A 4.9pJ/b 16-to-64Gb/s PAM-4 VSR transceiver in 28nm FDSOI CMOS

Emanuele Depaoli, Enrico Monaco, Giovanni Steffan, Marco Mazzini, Hongyang Zhang, Walter Audoglio, Oscar Belotti, Augusto Andrea Rossi, Guido Albasini, Massimo Pozzoni, Simone Erba, Andrea Mazzanti. A 4.9pJ/b 16-to-64Gb/s PAM-4 VSR transceiver in 28nm FDSOI CMOS. In 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018. pages 112-114, IEEE, 2018. [doi]

@inproceedings{DepaoliMSMZABRA18,
  title = {A 4.9pJ/b 16-to-64Gb/s PAM-4 VSR transceiver in 28nm FDSOI CMOS},
  author = {Emanuele Depaoli and Enrico Monaco and Giovanni Steffan and Marco Mazzini and Hongyang Zhang and Walter Audoglio and Oscar Belotti and Augusto Andrea Rossi and Guido Albasini and Massimo Pozzoni and Simone Erba and Andrea Mazzanti},
  year = {2018},
  doi = {10.1109/ISSCC.2018.8310209},
  url = {https://doi.org/10.1109/ISSCC.2018.8310209},
  researchr = {https://researchr.org/publication/DepaoliMSMZABRA18},
  cites = {0},
  citedby = {0},
  pages = {112-114},
  booktitle = {2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018},
  publisher = {IEEE},
  isbn = {978-1-5090-4940-0},
}