An algorithmic approach to optimizing fault coverage for BIST logic synthesis

Srinivas Devadas, Kurt Keutzer. An algorithmic approach to optimizing fault coverage for BIST logic synthesis. In Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998. pages 164, IEEE Computer Society, 1998. [doi]

@inproceedings{DevadasK98,
  title = {An algorithmic approach to optimizing fault coverage for BIST logic synthesis},
  author = {Srinivas Devadas and Kurt Keutzer},
  year = {1998},
  url = {http://www.computer.org/proceedings/itc/5093/50930164abs.htm},
  tags = {optimization, logic, coverage, systematic-approach},
  researchr = {https://researchr.org/publication/DevadasK98},
  cites = {0},
  citedby = {0},
  pages = {164},
  booktitle = {Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998},
  publisher = {IEEE Computer Society},
  isbn = {0-7803-5093-6},
}