V. R. Devanathan, Sunil Bhavsar, Rajat Mehrotra. Physical-Aware Memory BIST Datapath Synthesis: Architecture and Case-Studies on Complex SoCs. In Proceedings of the 20th IEEE Asian Test Symposium, ATS 2011, New Delhi, India, November 20-23, 2011. pages 457-458, IEEE Computer Society, 2011. [doi]
@inproceedings{DevanathanBM11,
title = {Physical-Aware Memory BIST Datapath Synthesis: Architecture and Case-Studies on Complex SoCs},
author = {V. R. Devanathan and Sunil Bhavsar and Rajat Mehrotra},
year = {2011},
doi = {10.1109/ATS.2011.102},
url = {http://doi.ieeecomputersociety.org/10.1109/ATS.2011.102},
researchr = {https://researchr.org/publication/DevanathanBM11},
cites = {0},
citedby = {0},
pages = {457-458},
booktitle = {Proceedings of the 20th IEEE Asian Test Symposium, ATS 2011, New Delhi, India, November 20-23, 2011},
publisher = {IEEE Computer Society},
isbn = {978-1-4577-1984-4},
}