V. R. Devanathan, Sunil Bhavsar, Rajat Mehrotra. Physical-Aware Memory BIST Datapath Synthesis: Architecture and Case-Studies on Complex SoCs. In Proceedings of the 20th IEEE Asian Test Symposium, ATS 2011, New Delhi, India, November 20-23, 2011. pages 457-458, IEEE Computer Society, 2011. [doi]
Abstract is missing.