V. R. Devanathan, Lakshmanan Balasubramanian, Rubin A. Parekhji. New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation. In 28th International Conference on VLSI Design, VLSID 2015, Bangalore, India, January 3-7, 2015. pages 363-368, IEEE Computer Society, 2015. [doi]
@inproceedings{DevanathanBP15,
title = {New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation},
author = {V. R. Devanathan and Lakshmanan Balasubramanian and Rubin A. Parekhji},
year = {2015},
doi = {10.1109/VLSID.2015.67},
url = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2015.67},
researchr = {https://researchr.org/publication/DevanathanBP15},
cites = {0},
citedby = {0},
pages = {363-368},
booktitle = {28th International Conference on VLSI Design, VLSID 2015, Bangalore, India, January 3-7, 2015},
publisher = {IEEE Computer Society},
isbn = {978-1-4799-6658-5},
}