Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms - researchr publication

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V. R. Devanathan, C. P. Ravikumar, V. Kamakoti. Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms. In 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India. pages 351-356, IEEE Computer Society, 2007. [doi]

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