A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction - researchr publication authors

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V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti. A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction. J. Low Power Electronics, 4(1):101-110, 2008. [doi]

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