V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti. A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction. J. Low Power Electronics, 4(1):101-110, 2008. [doi]
@article{DevanathanRMK08,
title = {A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction},
author = {V. R. Devanathan and C. P. Ravikumar and Rajat Mehrotra and V. Kamakoti},
year = {2008},
doi = {10.1166/jolpe.2008.150},
url = {http://dx.doi.org/10.1166/jolpe.2008.150},
tags = {architecture, testing, C++},
researchr = {https://researchr.org/publication/DevanathanRMK08},
cites = {0},
citedby = {0},
journal = {J. Low Power Electronics},
volume = {4},
number = {1},
pages = {101-110},
}