A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction

V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti. A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction. J. Low Power Electronics, 4(1):101-110, 2008. [doi]

Abstract

Abstract is missing.