An FPGA based Tiled Systolic Array Generator to Accelerate CNNs - researchr publication

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Veerendra S. Devaraddi, Nanditha Rao. An FPGA based Tiled Systolic Array Generator to Accelerate CNNs. In 25th Euromicro Conference on Digital System Design, DSD 2022, Maspalomas, Spain, August 31 - Sept. 2, 2022. pages 316-323, IEEE, 2022. [doi]

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