Table of Contents

• Message from the Program Chairs: DSD 2022Himar Fabelo, Samuel Ortega. [doi]
• Keynote SpeakersMartin Schoeberl. [doi]
• Evaluation of Early-exit Strategies in Low-cost FPGA-based Binarized Neural NetworksMinxuan Kong, Kris Nikov, José Luis Núñez-Yáñez. 1-8 [doi]
• A Supervisory Control Approach for Scheduling Real-time Periodic Tasks on Dynamically Reconfigurable PlatformsCherinet Kejela, Rajesh Devaraj, Arnab Sarkar, Sangeet Saha. 1-8 [doi]
• Message from the General Chair DSD 2022Gustavo Marrero Callicó. 1 [doi]
• Towards Hardware Support for FPGA Resource ElasticityAhsan Javed Awan. 9-15 [doi]
• Analysis of Graph Processing in Reconfigurable Devices for Edge Computing ApplicationsKaan Olgu, Kris Nikov, José L. Núñez-Yáñez. 16-23 [doi]
• moreMCU: A Runtime-reconfigurable RISC-V Platform for Sustainable Embedded SystemsTobias Scheipel, Florian Angermair, Marcel Baunach. 24-31 [doi]
• EARL: An Efficient Approximate HaRdware Framework for AcceLerating Fault Tree AnalysisSalar Hashemi, Amir M. Hajisadeghi, Hamid R. Zarandi. 32-38 [doi]
• ESAS: Exponent Series based Approximate Square Root DesignOmkar G. Ratnaparkhi, Madhav Rao. 39-45 [doi]
• An Approximate Carry Disregard Multiplier with Improved Mean Relative Error Distance and Probability of CorrectnessN. Amirafshar, A. S. Baroughi, H. S. Shahhoseini, Nima Taherinejad. 46-52 [doi]
• A Majority-based Approximate Adder for FPGAsBehnam Ghavami, Mahdi Sajedi, Mohsen Raji, Zhenman Fang, Lesley Shannon. 53-59 [doi]
• AxE: An Approximate-Exact Multi-Processor System-on-Chip PlatformA. S. Baroughi, Sini Huemer, H. S. Shahhoseini, Nima Taherinejad. 60-66 [doi]
• ImageSpec: Efficient High-Level Synthesis of Image Processing ApplicationsAbdul Khader Thalakkattu Moosa, Nilotpola Sarma, Chandan Karfa. 67-74 [doi]
• High-Level Synthesis of Geant4 Particle Transport Application for FPGARamakant Joshi, Kuruvilla Varghese. 75-83 [doi]
• A YOLO v3-tiny FPGA Architecture using a Reconfigurable Hardware Accelerator for Real-time Region of Interest DetectionViktor Herrmann, Justin Knapheide, Fritjof Steinert, Benno Stabernack. 84-92 [doi]
• PositIV: A Configurable Posit Processor Architecture for Image and Video ProcessingAkshat Ramachandran, John Gustafson, Anusua Roy, Rizwan Ahmed Ansari, Rohin D. Daruwala. 93-100 [doi]
• A Low-complexity FPGA TDC based on a DSP Delay Line and a Wave Union LauncherZijie Wang, Jiajun Lu, José L. Núñez-Yáñez. 101-108 [doi]
• FP-SLIC: A Fully-Pipelined FPGA Implementation of Superpixel Image SegmentationAdnan Ghaderi, Carl Ahlberg, Magnus Östgren, Fredrik Ekstrand, Mikael Ekström. 109-117 [doi]
• Skeptical Dynamic Dependability Management for Automated SystemsFabio Arnez, Guillaume Ollier, Ansgar Radermacher, Morayo Adedjouma, Simos Gerasimou, Chokri Mraidha, François Terrier. 118-125 [doi]
• Energy-Efficient Radix-4 Belief Propagation Polar Code Decoding Using an Efficient Sign-Magnitude Adder and Clock GatingOguz Meteer, Arvid B. Van Den Brink, Marco Jan Gerrit Bekooij. 126-133 [doi]
• Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-StudySallar Ahmadi-Pour, Sangeet Saha, Vladimir Herdt, Rolf Drechsler, Klaus D. McDonald-Maier. 134-141 [doi]
• X-on-X: Distributed Parallel Virtual Platforms for Heterogeneous SystemsLukas Jünger 0001, Simon Winther, Rainer Leupers. 142-148 [doi]
• Placement of Chains of Real-Time Tasks on Heterogeneous Platforms under EDF SchedulingDaniel Casini, Alessandro Biondi. 149-156 [doi]
• Prebypass: Software Register File Bypassing for Reduced Interconnection ArchitecturesKanishkan Vadivel, Barry de Bruin, Roel Jordans, Henk Corporaal, Pekka Jääskeläinen. 157-164 [doi]
• Decomposition of transition systems into sets of synchronizing Free-choice Petri NetsViktor Teren, Jordi Cortadella, Tiziano Villa. 165-173 [doi]
• Adaptive Exploration Based Routing for Spatial Isolation in Mixed Criticality SystemsNidhi Anantharajaiah, Jürgen Becker 0001. 174-180 [doi]
• A Hybrid Scheduling Mechanism for Multi-programming in Mixed-Criticality SystemsMohammad Bawatna, Behnaz Ranjbar, Akash Kumar 0001. 181-188 [doi]
• Hardware Support for Predictable Resource Sharing in Virtualized Heterogeneous MulticoresTimo Sandmann, Jürgen Becker 0001. 189-196 [doi]
• Inference Time Reduction of Deep Neural Networks on Embedded Devices: A Case StudyIsma-Ilou Sadou, Seyed Morteza Nabavinejad, Zhonghai Lu, Masoumeh Ebrahimi. 205-213 [doi]
• PosAx-O: Exploring Operator-level Approximations for Posit Arithmetic in Embedded AI/MLAmritha Immaneni, Salim Ullah, Suresh Nambi, Siva Satyendra Sahoo, Akash Kumar 0001. 214-223 [doi]
• A Clustering-Based Scoring Mechanism for Malicious Model Detection in Federated LearningCem Caglayan, Arda Yurdakul. 224-231 [doi]
• A Resilient System Design to Boot a RISC-V MPSoCAntti Nurmi, Antti Rautakoura, Henri Lunnikivi, Timo D. Hämäläinen. 232-238 [doi]
• RISC-V Core with Approximate Multiplier for Error-Tolerant ApplicationsAnu Verma, Priyamvada Sharma, Bishnu Prasad Das. 239-246 [doi]
• Suitability of ISAs for Data Paths Based on Redundant Number Systems: Is RISC-V the best?Johannes Knödtel, Sebastian Rachuj, Marc Reichenbach. 247-253 [doi]
• Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOIVíctor Soria Pardos, Max Doblas, Guillem López-Paradís, Gerard Candón, Narcís Rodas, Xavier Carril, Pau Fontova-Musté, Neiel Leyva, Santiago Marco-Sola, Miquel Moretó. 254-261 [doi]
• Coherency Traffic Reduction in Manycore SystemsErdem Derebasoglu, Ismail Kadayif, Ozcan Ozturk 0001. 262-267 [doi]
• Investigating Novel 3D Modular Schemes for Large Array Topologies: Power Modeling and Prototype FeasibilityPakon Thuphairo, Christopher Bailey 0002, Anthony Moulds, Jim Austin. 268-275 [doi]
• Ballast: Implementation of a Large MP-SoC on 22nm ASIC TechnologyAntti Rautakoura, Timo Hämäläinen 0001, Ari Kulmala, Tero Lehtinen, Mehdi Duman, Mohamed Ibrahim. 276-283 [doi]
• Hardware architecture for high throughput event visual data filtering with matrix of IIR filters algorithmMarcin Kowalczyk, Tomasz Kryjak. 284-291 [doi]
• Open-Source Research on Time-predictable Computer ArchitectureMartin Schoeberl. 292-297 [doi]
• PipeEdge: Pipeline Parallelism for Large-Scale Model Inference on Heterogeneous Edge DevicesYang Hu, Connor Imes, Xuanang Zhao, Souvik Kundu 0002, Peter A. Beerel, Stephen P. Crago, John Paul Walters. 298-307 [doi]
• Co-Optimizing Sensing and Deep Machine Learning in Automotive Cyber-Physical SystemsJoydeep Dey, Sudeep Pasricha. 308-315 [doi]
• An FPGA based Tiled Systolic Array Generator to Accelerate CNNsVeerendra S. Devaraddi, Nanditha Rao. 316-323 [doi]
• CPU-GPU Layer-Switched Low Latency CNN InferenceEhsan Aghapour, Dolly Sapra, Andy D. Pimentel, Anuj Pathania. 324-331 [doi]
• MVSTT: A Multi-Value Computation-in-Memory based on Spin-Transfer Torque MemoriesAtousa Jafari, Mahta Mayahinia, Soyed Tuhin Ahmed, Christopher Münch, Mehdi B. Tahoori. 332-339 [doi]
• TextBack: Watermarking Text Classifiers using BackdooringNandish Chattopadhyay, Rajan Kataria, Anupam Chattopadhyay. 340-347 [doi]
• Hardware-Software Codesign of a CNN AcceleratorChangjae Yi, Donghyun Kang, Soonhoi Ha. 348-356 [doi]
• SNAP: Selective NTV Heterogeneous Architectures for Power-Efficient Edge ComputingRafael Billig Tonetto, Antonio Carlos Schneider Beck, Gabriel L. Nazar. 357-364 [doi]
• Hardware Accelerator and Neural Network Co-Optimization for Ultra-Low-Power Audio Processing DevicesChristoph Gerum, Adrian Frischknecht, Tobias Hald, Paul Palomero Bernardo, Konstantin Lübeck, Oliver Bringmann 0001. 365-369 [doi]
• Quantization: how far should we go?Floran de Putter, Henk Corporaal. 373-382 [doi]
• Breaking (and Fixing) Channel-based Cryptographic Key Generation: A Machine Learning ApproachIhsen Alouani. 383-390 [doi]
• CaW-NAS: Compression Aware Neural Architecture SearchHadjer Benmeziane, Hamza Ouranoughi, Smaïl Niar, Kaoutar El Maghraoui. 391-397 [doi]
• Co-Optimization of DNN and Hardware Configurations on Edge GPUsHalima Bouzidi, Hamza Ouarnoughi, Smaïl Niar, El-Ghazali Talbi, Abdessamad Ait El Cadi. 398-405 [doi]
• Hardware Acceleration of Deep Neural Networks for Autonomous Driving on FPGA-based SoCGerlando Sciangula, Francesco Restuccia, Alessandro Biondi, Giorgio C. Buttazzo. 406-414 [doi]
• ARTS: An adaptive regularization training schedule for activation sparsity explorationZeqi Zhu, Arash Pourtaherian, Luc Waeijen, Lennart Bamberg, Egor Bondarev, Orlando Moreira. 415-422 [doi]
• RRAM-based Neuromorphic Computing: Data Representation, Architecture, Logic, and ProgrammingGrace Li Zhang, Shuhang Zhang, Hai Helen Li, Ulf Schlichtmann. 423-428 [doi]
• Partial Evaluation in Junction TreesMartin Roa Villescas, Patrick W. A. Wijnings, Sander Stuijk, Henk Corporaal. 429-437 [doi]
• DNAsim: Evaluation Framework for Digital Neuromorphic ArchitecturesSherif Eissa, Sander Stuijk, Henk Corporaal. 438-445 [doi]
• Demystifying the TensorFlow Eager Execution of Deep Learning Inference on a CPU-GPU TandemPaul Delestrac, Lionel Torres, David Novo. 446-455 [doi]
• A CFI Verification System based on the RISC-V Instruction Trace EncoderAnthony Zgheib, Olivier Potin, Jean-Baptiste Rigaud, Jean-Max Dutertre. 456-463 [doi]
• Variable-Length Instruction Set: Feature or Bug?Ihab Alshaer, Brice Colombier, Christophe Deleuze, Vincent Beroulle, Paolo Maistri. 464-471 [doi]
• Towards Fine-grained Side-Channel Instruction Disassembly on a System-on-ChipJulien Maillard, Thomas Hiscock, Maxime Lecomte, Christophe Clavier. 472-479 [doi]
• Combination of ROP Defense Mechanisms for Better Safety and Security in Embedded SystemsKai Lehniger, Mario Schölze, Jonas Jelonek, Peter Tabatt, Marcin Aftowicz, Peter Langendörfer. 480-487 [doi]
• Side-Channel Analysis of Saber KEM Using Amplitude-Modulated EM EmanationsRuize Wang, Kalle Ngo, Elena Dubrova. 488-495 [doi]
• Be My Guess: Guessing Entropy vs. Success Rate for Evaluating Side-Channel Attacks of Secure ChipsJulien Beguinot, Wei Cheng 0003, Sylvain Guilley, Olivier Rioul. 496-503 [doi]
• Open Source Hardware Design and Hardware Reverse Engineering: A Security AnalysisJohanna Baehr, Alexander Hepp, Michaela Brunner, Maja Malenko, Georg Sigl. 504-512 [doi]
• Implementation of the Rainbow signature scheme on SoC FPGATomás Preucil, Petr Socha, Martin Novotný. 513-519 [doi]
• Electromagnetic Leakage Assessment of a Proven Higher-Order Masking of AES S-BoxNicolas Bordes, Paolo Maistri. 520-527 [doi]
• Efficient Modular Polynomial Multiplier for NTT Accelerator of Crystals-KyberYuma Itabashi, Rei Ueno, Naofumi Homma. 528-533 [doi]
• On the Characterization of Jitter in Ring Oscillators using Allan variance for True Random Number Generator ApplicationsL. Benea, M. Carmona, Florian Pebay-Peyroula, R. Wacquez. 534-538 [doi]
• FPGA implementation of BIKE for quantum-resistant TLSAndrea Galimberti, Davide Galli, Gabriele Montanaro, William Fornaciari, Davide Zoni. 539-547 [doi]
• Evaluating Cryptographic Extensions On A RISC-V Simulation EnvironmentParangat Sud, Shekoufeh Neisarian, Elif Bilge Kavun. 548-555 [doi]
• SecDec: Secure Decode Stage thanks to masking of instructions with the generated signalsGaëtan Leplus, Olivier Savry, Lilian Bossuet. 556-563 [doi]
• Mobile Systems Secure State ManagementPaolo Amato, Niccolò Izzo, Carlo Meijer. 564-571 [doi]
• In vitro Testbed Platform for Evaluating Small Volume Contrast Agents via Magnetic Resonance ImagingMireia Perera-Gonzalez, Kristine Y. Ma, Chris A. Flask, Heather A. Clark. 572-576 [doi]
• CELR: Cloud Enhanced Local Reconstruction from low-dose sparse Scanning Electron Microscopy imagesFloran de Putter, Maurice Peemen, Pavel Potocek, Remco Schoenmakers, Henk Corporaal. 577-584 [doi]
• A Smart Floor Device of an Exergame Platform for Elderly Fall Prevention: *Note: Sub-titles are not captured in Xplore and should not be usedChristos Goumopoulos, Damianos Ougkrenidis, Dimitris Gklavakis, Iraklis Ioannidis. 585-592 [doi]
• GPU Based Implementation for the Pre-Processing of Radar-Based Human Activity RecognitionAlexandre Bordat, Petr Dobiás, Julien Le Kernec, David Guyard, Olivier Romain. 593-598 [doi]
• On the Validation of Multi-Level Personalised Health Condition ModelNajma Taimoor, Semeen Rehman. 599-606 [doi]
• Towards Skin Cancer Self-Monitoring through an Optimized MobileNet with Coordinate AttentionMaría Castro-Fernández, Abián Hernández, Himar Fabelo, Francisco Balea-Fernández, Samuel Ortega, Gustavo Marrero Callicó. 607-614 [doi]
• Event-Driven Programming of FPGA-accelerated ROS 2 Robotics ApplicationsChristian Lienen, Marco Platzner. 615-623 [doi]
• Real-Time Polling Task: Design and AnalysisBenoit Varillon, David Doose. 624-631 [doi]
• Design Space Exploration for Distributed Cyber-Physical Systems: State-of-the-art, Challenges, and DirectionsMarius Herget, Faezeh Sadat Saadatmand, Martin Bor, Ignacio González Alonso, Todor P. Stefanov, Benny Akesson, Andy D. Pimentel. 632-640 [doi]
• How are Industry 4.0 Reference Architectures Used in CPPS Development?David Haunschmied, Udo Kannengiesser. 641-648 [doi]
• Monitoring Framework to Support Mixed-Criticality Applications on Multicore PlatformsGautam Gala, Carlos Rodriguez, Veaceslav Monaco, Javier Castillo, Gerhard Fohler, Veaceslav Falico, Sergey Tverdyshev. 649-656 [doi]
• Towards Resilient QDI Pipeline ImplementationsZaheer Tabassam, Andreas Steininger. 657-664 [doi]
• Nonlinear Compression Block Codes Search StrategyOndrej Novák. 665-670 [doi]
• IMMizer: An Innovative Cost-Effective Method for Minimizing Assertion SetsMohammad Reza Heidari Iman, Jaan Raik, Gert Jervan, Tara Ghasempouri. 671-678 [doi]
• Verifying Liveness and Real-Time of OS-Based Embedded SoftwareLeandro Batista Ribeiro, Drona Nagarajan, Vignesh Manjunath, Muhammad Tanveer Ali Ahmad, Marcel Baunach. 679-688 [doi]
• Verification of Calculations of Non-Homogeneous Markov Chains Using Monte Carlo SimulationJan Reznícek, Martin Kohlík, Hana Kubátová. 689-695 [doi]
• Towards a Real-Time Smart Prognostics and Health Management (PHM) of Safety Critical Embedded SystemsJuliano Pimentel, Alistair A. McEwan, Hong Qing Yu. 696-703 [doi]
• A holistic hardware-software approach for fault-aware embedded systemsFabian Kempf, Christoph Kühbacher, Christian Mellwig, Sebastian Altmeyer, Theo Ungerer, Jürgen Becker 0001. 704-711 [doi]
• RED-SEA: Network Solution for Exascale ArchitecturesAndrea Biagioni, Paolo Cretaro, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Pier Stanislao Paolucci, Elena Pastorelli, Francesco Simula, Matteo Turisini, Piero Vicini, Roberto Ammendola, Pascale Bernier-Bruna, Claire Chen, Said Derradji, Stéphane Guez, Pierre-Axel Lagadec, Gregoire Pichon, Etienne WALTER, Gaetan De Gassowski, Matthieu Hautreaux, Stephane Mathieu, Gilles Moreau, Marc Pérache, Hugo Taboada, Torsten Hoefler, Timo Schneider, Matteo Barnaba, Giuseppe Piero Brandino, Francesco De Giorgi, Matteo Poggi, Iakovos Mavroidis, Yannis Papaefstathiou, Nikolaos Tampouratzis, Benjamin Kalisch, Ulrich Krackhardt, Mondrian Nuessle, Pantelis Xirouchakis, Vangelis Mageiropoulos, Michalis Gianioudis, Harisis Loukas, Aggelos Ioannou, Nikos Kallimanis, Nikos Chrysos, Manolis Katevenis, Wolfang Frings, Dominik Gottwald, Felime Guimaraes, Max Holicki, Volker Marx, Yannik Muller, Carsten Clauss, Hugo Falter, Xu Huang, Jennifer Lopez Barillao, Thomas Moschny, Simon Pickartz, Francisco J. Alfaro, Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles, Jose L. Sanchez, Adrián Castelló, Jose Duro, Maria Engracia Gomez, Enrique Quintana, Julio Sahuquillo, Eugenio Stabile. 712-719 [doi]
• Abeto framework: a Solution for Heterogeneous IP ManagementAntonio J. Sánchez, Yubal Barrios, Diego Ventura, Lucana Santos, Roberto Sarmiento. 720-725 [doi]
• Sense and Control of Oscillating MEMS MirrorsNorbert Druml, Philipp Greiner, Ievgeniia Maksymova, Leonhard Christian Niedermueller. 726-732 [doi]
• COMP4DRONES: Key Enabling Technologies for Drones to enhance Mobility and Logistics OperationsRéda Nouacer, Raphaël Lallement, Rodrigo Castiñcira, Jean-Frédéric Real, Jean-Patrick Mascomère. 733-740 [doi]
• Sentient Spaces: Intelligent Totem Use Case in the ECSEL FRACTAL ProjectFederica Caruso, Tania Di Mascio, Daniele Frigioni, Luigi Pomante, Giacomo Valente, Stefano Delucchi, Paolo Burgio, Manuel Di Frangia, Luca Paganin, Chiara Garibotto, Damiano Vallocchia. 741-747 [doi]
• Network on Privacy-Aware Audio-and Video-Based Applications for Active and Assisted Living: GoodBrother ProjectNicolas Sklavos 0001, Maria Pantopoulou, Francisco Flórez-Revuelta. 748-753 [doi]
• SmartDelta: Automated Quality Assurance and Optimization in Incremental Industrial Software Systems DevelopmentMehrdad Saadatmand, Eduard Paul Enoiu, Holger Schlingloff, Michael Felderer, Wasif Afzal. 754-760 [doi]
• Polynomial Formal Verification of Approximate AddersMartha Schnieber, Saman Fröhlich, Rolf Drechsler. 761-768 [doi]
• SAT-based Exact Synthesis of Ternary Reversible Circuits using a Functionally Complete Gate LibraryAbhoy Kole, Kamalika Datta, Indranil Sengupta 0001, Rolf Drechsler. 769-776 [doi]
• Optimizing Lattice-based Post-Quantum Cryptography Codes for High-Level SynthesisAndrea Guerrieri, Gabriel Da Silva Marques, Francesco Regazzoni 0001, Andres Upegui. 777-784 [doi]
• Designing Approximate Arithmetic Circuits with Combined Error ConstraintsMilan Ceska 0001, Jirí Matyás, Vojtech Mrazek, Tomás Vojnar. 785-792 [doi]
• Unlocking Sneak Path Analysis in Memristor Based Logic Design StylesKamalika Datta, Saeideh Shirinzadeh, Phrangboklang Lyngton Thangkhiew, Indranil Sengupta 0001, Rolf Drechsler. 793-800 [doi]
• Technology Mapping for PAIG Optimised Polymorphic CircuitsRichard Ruzicka, Václav Simek. 801-808 [doi]
• MEDA Biochip based Single- Target Fluidic Mixture Preparation with Minimum WastageDebraj Kundu, Sudip Roy 0001. 809-814 [doi]
• Generation of Verified Programs for In-Memory ComputingSaman Fröhlich, Rolf Drechsler. 815-820 [doi]
• SMART: Investigating the Impact of Threshold Voltage Suppression in an In-SRAM Multiplication/Accumulation Accelerator for Accuracy Improvement in 65 nm CMOS TechnologySaeed Seyedfaraji, Baset Mesgari, Semeen Rehman. 821-826 [doi]
• Evaluation of artificial neural networks for the detection of esophagus tumor cells in microscopic hyperspectral imagesAnna Schröder, Marianne Maktabi, René Thieme, Boris Jansen-Winkeln, Ines Gockel, Claire Chalopin. 827-834 [doi]
• Hyperparameter Optimization for Brain Tumor Classification with Hyperspectral ImagesAlberto Martín-Pérez, Manuel Villa, Guillermo Vázquez, Jaime Sancho, Gonzalo Rosa, Pallab Sutradhar, Miguel Chavarrías, Alfonso Lagares, Eduardo Juárez, César Sanz. 835-842 [doi]
• Glioblastoma Classification in Hyperspectral Images by Nonlinear UnmixingJuan N. Mendoza-Chavarría, Eric R. Zavala-Sánchez, Liliana Granados-Castro, Inés A. Cruz-Guerrero, Himar Fabelo, Samuel Ortega, Gustavo Marrero Callicó, Daniel U. Campos-Delgado. 843-848 [doi]
• Estimation of deoxygenated and oxygenated hemoglobin by multispectral blind linear unmixingLiliana Granados-Castro, Omar Gutierrez-Navarro, Inés A. Cruz-Guerrero, Juan N. Mendoza-Chavarría, Eric R. Zavala-Sánchez, Daniel U. Campos-Delgado. 849-854 [doi]
• Reflectance Calibration with Normalization Correction in Hyperspectral ImagingInés A. Cruz-Guerrero, Raquel Leon, Liliana Granados-Castro, Himar Fabelo, Samuel Ortega, Daniel U. Campos-Delgado, Gustavo Marrero Callicó. 855-862 [doi]
• Development of a Hyperspectral Colposcope for Early Detection and Assessment of Cervical DysplasiaCarlos Vega, Raquel León, Norberto Medina, Himar Fabelo, Samuel Ortega, Fran Balea, Aday García, Margarita Medina, Silvia De León, Alicia Martín, Gustavo Marrero Callicó. 863-870 [doi]
• Attention-based Skin Cancer Classification Through Hyperspectral ImagingMarco La Salvia, Emanuele Torti, Marco Gazzoni, Elisa Marenzi, Raquel Leon, Samuel Ortega, Himar Fabelo, Gustavo Marrero Callicó, Francesco Leporati. 871-876 [doi]
• A resolution method in case of air congestion: rerouting and/or ground holding approachLudovica Adacher, Marta Flamini. 877-884 [doi]
• Optimizing UAV location awareness telemetry data for Low Power Wide Area NetworkTheodoros Karachalios, Christos Xouris, Theofanis Orphanoudakis. 885-888 [doi]
• POLAR: Performance-aware On-device Learning Capable Programmable Processing-in-Memory Architecture for Low-Power ML ApplicationsSathwika Bavikadi, Purab Ranjan Sutradhar, Mark Indovina, Amlan Ganguly, Sai Manoj Pudukotai Dinakarrao. 889-898 [doi]
• Blind Data Adversarial Bit-flip Attack against Deep Neural NetworksBehnam Ghavami, Mani Sadati, Mohammad Shahidzadeh, Zhenman Fang, Lesley Shannon. 899-904 [doi]
• Hybrid Post-Quantum Enhanced TLS 1.3 on Embedded DevicesDominik Marchsreiter, Johanna Sepúlveda. 905-912 [doi]
• A Framework for Evaluating Connected Vehicle Security against False Data Injection AttacksIpsita Koley, Sunandan Adhikary, Rohit Rohit, Soumyajit Dey. 913-920 [doi]
• Is the Whole lesser than its Parts? Breaking an Aggregation based Privacy aware Metering AlgorithmSoumyadyuti Ghosh, Urbi Chatterjee, Soumyajit Dey, Debdeep Mukhopadhyay. 921-929 [doi]