Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan. FPGA Accelerated FPGA Placement. In Ioannis Sourdis, Christos-Savvas Bouganis, Carlos Álvarez 0001, Leonel Toledo, Pedro Valero-Lara, Xavier Martorell, editors, 29th International Conference on Field Programmable Logic and Applications, FPL 2019, Barcelona, Spain, September 8-12, 2019. pages 404-410, IEEE, 2019. [doi]
@inproceedings{DharSIP19-0,
title = {FPGA Accelerated FPGA Placement},
author = {Shounak Dhar and Love Singhal and Mahesh A. Iyer and David Z. Pan},
year = {2019},
doi = {10.1109/FPL.2019.00070},
url = {https://doi.org/10.1109/FPL.2019.00070},
researchr = {https://researchr.org/publication/DharSIP19-0},
cites = {0},
citedby = {0},
pages = {404-410},
booktitle = {29th International Conference on Field Programmable Logic and Applications, FPL 2019, Barcelona, Spain, September 8-12, 2019},
editor = {Ioannis Sourdis and Christos-Savvas Bouganis and Carlos Álvarez 0001 and Leonel Toledo and Pedro Valero-Lara and Xavier Martorell},
publisher = {IEEE},
isbn = {978-1-7281-4884-7},
}