Jonas Diemer, Daniel Thiele, Rolf Ernst. Formal worst-case timing analysis of Ethernet topologies with strict-priority and AVB switching. In 7th IEEE International Symposium on Industrial Embedded Systems, SIES 2012, Karlsruhe, Germany, June 20-22, 2012. pages 1-10, IEEE, 2012. [doi]
@inproceedings{DiemerTE12,
title = {Formal worst-case timing analysis of Ethernet topologies with strict-priority and AVB switching},
author = {Jonas Diemer and Daniel Thiele and Rolf Ernst},
year = {2012},
doi = {10.1109/SIES.2012.6356564},
url = {http://dx.doi.org/10.1109/SIES.2012.6356564},
researchr = {https://researchr.org/publication/DiemerTE12},
cites = {0},
citedby = {0},
pages = {1-10},
booktitle = {7th IEEE International Symposium on Industrial Embedded Systems, SIES 2012, Karlsruhe, Germany, June 20-22, 2012},
publisher = {IEEE},
isbn = {978-1-4673-2685-8},
}