Markus Dietl, Puneet Sareen. A new low power and area efficient semi-digital PLL architecture for low bandwidth applications. In David Atienza, Yuan Xie, José L. Ayala, Ken S. Stevens, editors, Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, Lausanne, Switzerland, May 2-6, 2011. pages 363-366, ACM, 2011. [doi]
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