Wei Ding, Mahmut T. Kandemir, Diana Guttman, Adwait Jog, Chita R. Das, Praveen Yedlapalli. Trading cache hit rate for memory performance. In José Nelson Amaral, Josep Torrellas, editors, International Conference on Parallel Architectures and Compilation, PACT '14, Edmonton, AB, Canada, August 24-27, 2014. pages 357-368, ACM, 2014. [doi]
@inproceedings{DingKGJDY14,
title = {Trading cache hit rate for memory performance},
author = {Wei Ding and Mahmut T. Kandemir and Diana Guttman and Adwait Jog and Chita R. Das and Praveen Yedlapalli},
year = {2014},
doi = {10.1145/2628071.2628082},
url = {http://doi.acm.org/10.1145/2628071.2628082},
researchr = {https://researchr.org/publication/DingKGJDY14},
cites = {0},
citedby = {0},
pages = {357-368},
booktitle = {International Conference on Parallel Architectures and Compilation, PACT '14, Edmonton, AB, Canada, August 24-27, 2014},
editor = {José Nelson Amaral and Josep Torrellas},
publisher = {ACM},
isbn = {978-1-4503-2809-8},
}