Rostislav (Reuven) Dobkin, Michael Peleg, Ran Ginosar. Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders. IEEE Trans. VLSI Syst., 13(4):427-438, 2005. [doi]
@article{DobkinPG05,
title = {Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders},
author = {Rostislav (Reuven) Dobkin and Michael Peleg and Ran Ginosar},
year = {2005},
doi = {10.1109/TVLSI.2004.842916},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2004.842916},
tags = {architecture, design},
researchr = {https://researchr.org/publication/DobkinPG05},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {13},
number = {4},
pages = {427-438},
}