Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders

Rostislav (Reuven) Dobkin, Michael Peleg, Ran Ginosar. Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders. IEEE Trans. VLSI Syst., 13(4):427-438, 2005. [doi]

Abstract

Abstract is missing.