A 4 + 2T SRAM for Searching and In-Memory Computing With 0.3-V VDDmin

Qing Dong, Supreet Jeloka, Mehdi Saligane, Yejoong Kim, Masaru Kawaminami, Akihiko Harada, Satoru Miyoshi, Makoto Yasuda, David Blaauw, Dennis Sylvester. A 4 + 2T SRAM for Searching and In-Memory Computing With 0.3-V VDDmin. J. Solid-State Circuits, 53(4):1006-1015, 2018. [doi]

@article{DongJSKKHMYBS18,
  title = {A 4 + 2T SRAM for Searching and In-Memory Computing With 0.3-V VDDmin},
  author = {Qing Dong and Supreet Jeloka and Mehdi Saligane and Yejoong Kim and Masaru Kawaminami and Akihiko Harada and Satoru Miyoshi and Makoto Yasuda and David Blaauw and Dennis Sylvester},
  year = {2018},
  doi = {10.1109/JSSC.2017.2776309},
  url = {https://doi.org/10.1109/JSSC.2017.2776309},
  researchr = {https://researchr.org/publication/DongJSKKHMYBS18},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {53},
  number = {4},
  pages = {1006-1015},
}