Yazhuo Dong, Wu Zhan, Xiqing Ye. Pipeline template and scheduling algorithm for mapping multiple loop nests on FPGA with limited resources. In José Luis Ayala, Alex K. Jones, Patrick H. Madden, Ayse Kivilcim Coskun, editors, Great Lakes Symposium on VLSI 2013 (part of ECRC), GLSVLSI'13, Paris, France, May 2-4, 2013. pages 343-344, ACM, 2013. [doi]
@inproceedings{DongZY13,
title = {Pipeline template and scheduling algorithm for mapping multiple loop nests on FPGA with limited resources},
author = {Yazhuo Dong and Wu Zhan and Xiqing Ye},
year = {2013},
doi = {10.1145/2483028.2483134},
url = {http://doi.acm.org/10.1145/2483028.2483134},
researchr = {https://researchr.org/publication/DongZY13},
cites = {0},
citedby = {0},
pages = {343-344},
booktitle = {Great Lakes Symposium on VLSI 2013 (part of ECRC), GLSVLSI'13, Paris, France, May 2-4, 2013},
editor = {José Luis Ayala and Alex K. Jones and Patrick H. Madden and Ayse Kivilcim Coskun},
publisher = {ACM},
isbn = {978-1-4503-2032-0},
}