A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Cheng-Yan Du, Chieh-Fu Tsai, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang. A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow. In IEEE International Solid- State Circuits Conference, ISSCC 2023, San Francisco, CA, USA, February 19-23, 2023. pages 332-333, IEEE, 2023. [doi]

This author has not been identified. Look up 'Cheng-Yan Du' in GoogleThis author has not been identified. Look up 'Chieh-Fu Tsai' in GoogleThis author has not been identified. Look up 'Wen-Ching Chen' in GoogleThis author has not been identified. Look up 'Liang-Yi Lin' in GoogleThis author has not been identified. Look up 'Nian-Shyang Chang' in GoogleThis author has not been identified. Look up 'Chun-Pin Lin' in GoogleThis author has not been identified. Look up 'Chi-Shi Chen' in GoogleThis author has not been identified. Look up 'Chia-Hsiang Yang' in Google

runs on WebDSL