Cheng-Yan Du, Chieh-Fu Tsai, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang. A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow. In IEEE International Solid- State Circuits Conference, ISSCC 2023, San Francisco, CA, USA, February 19-23, 2023. pages 332-333, IEEE, 2023. [doi]
@inproceedings{DuTCLCLCY23,
title = {A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow},
author = {Cheng-Yan Du and Chieh-Fu Tsai and Wen-Ching Chen and Liang-Yi Lin and Nian-Shyang Chang and Chun-Pin Lin and Chi-Shi Chen and Chia-Hsiang Yang},
year = {2023},
doi = {10.1109/ISSCC42615.2023.10067774},
url = {https://doi.org/10.1109/ISSCC42615.2023.10067774},
researchr = {https://researchr.org/publication/DuTCLCLCY23},
cites = {0},
citedby = {0},
pages = {332-333},
booktitle = {IEEE International Solid- State Circuits Conference, ISSCC 2023, San Francisco, CA, USA, February 19-23, 2023},
publisher = {IEEE},
isbn = {978-1-6654-9016-0},
}