Yiwei Du, Jianshi Tang, Yijun Li, Yue Xi, Bin Gao 0006, He Qian, Huaqiang Wu. Monolithic 3D Integration of FeFET, Hybrid CMOS Logic and Analog RRAM Array for Energy-Efficient Reconfigurable Computing-In-Memory Architecture. In 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023. pages 1-2, IEEE, 2023. [doi]
@inproceedings{DuTLX0QW23,
title = {Monolithic 3D Integration of FeFET, Hybrid CMOS Logic and Analog RRAM Array for Energy-Efficient Reconfigurable Computing-In-Memory Architecture},
author = {Yiwei Du and Jianshi Tang and Yijun Li and Yue Xi and Bin Gao 0006 and He Qian and Huaqiang Wu},
year = {2023},
doi = {10.23919/VLSITechnologyandCir57934.2023.10185221},
url = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185221},
researchr = {https://researchr.org/publication/DuTLX0QW23},
cites = {0},
citedby = {0},
pages = {1-2},
booktitle = {2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023},
publisher = {IEEE},
isbn = {978-4-86348-806-9},
}