Architecture, Design, and Verification of an 18 Million Transistor Digital Television and Media Processor Chip

Santanu Dutta. Architecture, Design, and Verification of an 18 Million Transistor Digital Television and Media Processor Chip. In Dimitrios Soudris, Peter Pirsch, Erich Barke, editors, Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings. Volume 1918 of Lecture Notes in Computer Science, pages 225-232, Springer, 2000. [doi]

Abstract

Abstract is missing.