Bit level architectural exploration technique for the design of low power multipliers

George Economakos, K. Anagnostopoulos. Bit level architectural exploration technique for the design of low power multipliers. In International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece. IEEE, 2006. [doi]

Authors

George Economakos

This author has not been identified. Look up 'George Economakos' in Google

K. Anagnostopoulos

This author has not been identified. Look up 'K. Anagnostopoulos' in Google