Reduced Precision Checking for a Floating Point Adder

Patrick J. Eibl, Andrew D. Cook, Daniel J. Sorin. Reduced Precision Checking for a Floating Point Adder. In Dimitris Gizopoulos, Susumu Horiguchi, Spyros Tragoudas, Mohammad Tehranipoor, editors, 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, 7-9 October 2009, Chicago, Illinois, USA. pages 145-152, IEEE Computer Society, 2009. [doi]

Abstract

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