Praveen Elakkumanan, Kishan Prasad, Ramalingam Sridhar. Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic. In 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA. pages 617-624, IEEE Computer Society, 2006. [doi]
Abstract is missing.