A Spur-Frequency-Boosting PLL With a -74 dBc Reference-Spur Suppression in 90 nm Digital CMOS

Mohamed M. Elsayed, Mohammed M. Abdul-Latif, Edgar Sánchez-Sinencio. A Spur-Frequency-Boosting PLL With a -74 dBc Reference-Spur Suppression in 90 nm Digital CMOS. J. Solid-State Circuits, 48(9):2104-2117, 2013. [doi]

@article{ElsayedAS13,
  title = {A Spur-Frequency-Boosting PLL With a -74 dBc Reference-Spur Suppression in 90 nm Digital CMOS},
  author = {Mohamed M. Elsayed and Mohammed M. Abdul-Latif and Edgar Sánchez-Sinencio},
  year = {2013},
  doi = {10.1109/JSSC.2013.2266865},
  url = {http://dx.doi.org/10.1109/JSSC.2013.2266865},
  researchr = {https://researchr.org/publication/ElsayedAS13},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {48},
  number = {9},
  pages = {2104-2117},
}