Clock Driver Design for Low-Power High-Speed 90-nm CMOS Register Array - researchr publication references

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Tadayoshi Enomoto, Suguru Nagayama, Hiroaki Shikano, Yousuke Hagiwara. Clock Driver Design for Low-Power High-Speed 90-nm CMOS Register Array. IEICE Transactions, 91-C(4):553-561, 2008. [doi]

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