An Inherently Secure FPGA using PUF Hardware-Entanglement and Side-Channel Resistant Logic in 65nm Bulk CMOS

Burak Erbagci, Nail Etkin Can Akkaya, Cagri Erbagci, Ken Mai. An Inherently Secure FPGA using PUF Hardware-Entanglement and Side-Channel Resistant Logic in 65nm Bulk CMOS. In 45th IEEE European Solid State Circuits Conference, ESSCIRC 2019, Cracow, Poland, September 23-26, 2019. pages 65-68, IEEE, 2019. [doi]

@inproceedings{ErbagciAEM19,
  title = {An Inherently Secure FPGA using PUF Hardware-Entanglement and Side-Channel Resistant Logic in 65nm Bulk CMOS},
  author = {Burak Erbagci and Nail Etkin Can Akkaya and Cagri Erbagci and Ken Mai},
  year = {2019},
  doi = {10.1109/ESSCIRC.2019.8902789},
  url = {https://doi.org/10.1109/ESSCIRC.2019.8902789},
  researchr = {https://researchr.org/publication/ErbagciAEM19},
  cites = {0},
  citedby = {0},
  pages = {65-68},
  booktitle = {45th IEEE European Solid State Circuits Conference, ESSCIRC 2019, Cracow, Poland, September 23-26, 2019},
  publisher = {IEEE},
  isbn = {978-1-7281-1550-4},
}