Roger Espasa, Mateo Valero. Simultaneous multithreaded vector architecture: merging ILP and DLP for high performance. In Proceedings of the Fourth International on High-Performance Computing, HiPC 1997, Bangalore, India, 18-21 December, 1997. pages 350-357, IEEE Computer Society, 1997. [doi]
@inproceedings{EspasaV97-0,
title = {Simultaneous multithreaded vector architecture: merging ILP and DLP for high performance},
author = {Roger Espasa and Mateo Valero},
year = {1997},
doi = {10.1109/HIPC.1997.634514},
url = {http://doi.ieeecomputersociety.org/10.1109/HIPC.1997.634514},
researchr = {https://researchr.org/publication/EspasaV97-0},
cites = {0},
citedby = {0},
pages = {350-357},
booktitle = {Proceedings of the Fourth International on High-Performance Computing, HiPC 1997, Bangalore, India, 18-21 December, 1997},
publisher = {IEEE Computer Society},
isbn = {0-8186-8067-9},
}