Low-latency MAP demapper architecture for coded modulation with iterative decoding - researchr publication authors

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YouZhe Fan, Chi-Ying Tsui. Low-latency MAP demapper architecture for coded modulation with iterative decoding. In IEEE International Symposium on Circuits and Systemss, ISCAS 2014, Melbourne, Victoria, Australia, June 1-5, 2014. pages 730-733, IEEE, 2014. [doi]

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