A Sort-Less FPGA-Based Non-Maximum Suppression Accelerator using Multi-Thread Computing and Binary Max Engine for Object Detection - researchr publication authors

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Chaoming Fang, Habib Derbyshire, Wenyu Sun, Jinshan Yue, Haobing Shi, Yongpan Liu. A Sort-Less FPGA-Based Non-Maximum Suppression Accelerator using Multi-Thread Computing and Binary Max Engine for Object Detection. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2021, Busan, Korea, Republic of, November 7-10, 2021. pages 1-3, IEEE, 2021. [doi]

This author has not been identified. Look up 'Chaoming Fang' in GoogleThis author has not been identified. Look up 'Habib Derbyshire' in GoogleThis author has not been identified. Look up 'Wenyu Sun' in GoogleThis author has not been identified. Look up 'Jinshan Yue' in GoogleThis author has not been identified. Look up 'Haobing Shi' in GoogleThis author has not been identified. Look up 'Yongpan Liu' in Google

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