Balance power leakage to fight against side-channel analysis at gate level in FPGAs - researchr publication authors

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Xin Fang, Pei Luo, Yunsi Fei, Miriam Leeser. Balance power leakage to fight against side-channel analysis at gate level in FPGAs. In 26th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2015, Toronto, ON, Canada, July 27-29, 2015. pages 154-155, IEEE, 2015. [doi]

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