Abstract is missing.
- BlueDBM: A multi-access, distributed flash store for Big Data analyticsArvind. [doi]
- Accelerating data centers with reconfigurable logicDerek Chiou. [doi]
- Automatic design of domain-specific instructions for low-power processorsCecilia González-Alvarez, Jennifer B. Sartor, Carlos Álvarez, Daniel Jiménez-González, Lieven Eeckhout. 1-8 [doi]
- Custom FPGA-based soft-processors for sparse graph accelerationNachiket Kapre. 9-16 [doi]
- A soft-core processor array for relational operatorsRaphael Polig, Heiner Giefers, Walter Stechele. 17-24 [doi]
- Atomic stream computation unit based on micro-thread level parallelismNasim Farahini, Ahmed Hemani. 25-29 [doi]
- Timing speculation-aware instruction set extension for resource-constrained embedded systemsTanvir Ahmed, Yuko Hara-Azumi. 30-34 [doi]
- A GPU-based correlator X-engine implemented on the CHIME PathfinderNolan Denman, Mandana Amiri, Kevin Bandura, Liam Connor, Matt Dobbs, Mateus Fandino, Mark Halpern, Adam Hincks, Gary Hinshaw, Carolin Hofer, Peter Klages, Kiyoshi Masui, Juan Mena Parra, Laura Newburgh, Andre Recnik, J. Richard Shaw, Kris Sigurdson, Kendrick Smith, Keith Vanderlinde. 35-40 [doi]
- Power and performance trade-offs for Space Time Adaptive ProcessingNitin A. Gawande, Joseph B. Manzano, Antonino Tumeo, Nathan R. Tallent, Darren J. Kerbyson, Adolfy Hoisie. 41-48 [doi]
- Accelerating persistent scatterer pixel selection for InSAR processingTahsin Reza, Aaron Zimmer, Parwant Ghuman, Tanuj kr Aasawat, Matei Ripeanu. 49-56 [doi]
- An efficient real-time data pipeline for the CHIME Pathfinder radio telescope X-engineAndre Recnik, Kevin Bandura, Nolan Denman, Adam D. Hincks, Gary Hinshaw, Peter Klages, Ue-Li Pen, Keith Vanderlinde. 57-61 [doi]
- An IEEE 754 double-precision floating-point multiplier for denormalized and normalized floating-point numbersRoss Thompson, James E. Stine. 62-63 [doi]
- Dual-rail active protection system against side-channel analysis in FPGAsWei He, Dirmanto Jap. 64-65 [doi]
- Does arithmetic logic dominate data movement? a systematic comparison of energy-efficiency for FFT acceleratorsTung Thanh Hoang, Amirali Shambayati, Henry Hoffmann, Andrew A. Chien. 66-67 [doi]
- An FPGA implementation of a Restricted Boltzmann Machine classifier using stochastic bit streamsBingzhe Li, M. Hassan Najafi, David J. Lilja. 68-69 [doi]
- Application-set driven exploration for custom processor architecturesMehmet Ali Arslan, Flavius Gruian, Krzysztof Kuchcinski. 70-71 [doi]
- Speeding up graph-based SLAM algorithm: A GPU-based heterogeneous architecture studyAbdelhamid Dine, Abdelhafid Elouardi, Bastien Vincke, Samir Bouaziz. 72-73 [doi]
- Range reduction based on Pythagorean triples for trigonometric function evaluationHugues de Lassus Saint-Genies, David Defour, Guillaume Revy. 74-81 [doi]
- LightSpMV: Faster CSR-based sparse matrix-vector multiplication on CUDA-enabled GPUsYongchao Liu, Bertil Schmidt. 82-89 [doi]
- GPU-based multifrontal optimizing method in sparse Cholesky factorizationRan Zheng, Wei Wang, Hai Jin, Song Wu, Yong Chen, Han Jiang. 90-97 [doi]
- A metamorphotic Network-on-Chip for various types of parallel applicationsSeiichi Tade, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi. 98-105 [doi]
- Dynamic pipeline-partitioned video decoding on symmetric stream multiprocessorsMing-Ju Wu, Yan-Ting Chen, Chun-Jen Tsai. 106-110 [doi]
- Stochastic circuit design and performance evaluation of vector quantizationRan Wang, Jie Han, Bruce F. Cockburn, Duncan G. Elliott. 111-115 [doi]
- Mixed-signal implementation of differential decoding using binary message passing algorithmsGlenn Cowan, Kevin Cushon, Warren J. Gross. 116-119 [doi]
- Hardware acceleration of Private Information Retrieval protocols using GPUsMihai Maruseac, Gabriel Ghinita, Ming Ouyang, Razvan Rughinis. 120-127 [doi]
- Accelerating bootstrapping in FHEW using GPUsMoon Sung Lee, Yongje Lee, Jung Hee Cheon, Yunheung Paek. 128-135 [doi]
- Multi-task support for security-enabled embedded processorsTedy Thomas, Arman Pouraghily, Kekai Hu, Russell Tessier, Tilman Wolf. 136-143 [doi]
- Towards secure cryptographic software implementation against side-channel power analysis attacksPei Luo, Liwei Zhang, Yunsi Fei, A. Adam Ding. 144-148 [doi]
- Programmable RNS lattice-based parallel cryptographic decryptionPaulo Martins, Leonel Sousa, Julien Eynard, Jean-Claude Bajard. 149-153 [doi]
- Balance power leakage to fight against side-channel analysis at gate level in FPGAsXin Fang, Pei Luo, Yunsi Fei, Miriam Leeser. 154-155 [doi]
- How can Garbage Collection be energy efficient by dynamic offloading?Jie Tang, Chen Liu, Jean-Luc Gaudiot. 156-157 [doi]
- Automatic frame rate-based DVFS of gameZhinan Cheng, Xi Li, Beilei Sun, Ce Gao, Jiachen Song. 158-159 [doi]
- MultiExplorer: A tool set for multicore system-on-chip design explorationRodrigo Devigo, Liana Duenha, Rodolfo Azevedo, Ricardo Santos. 160-161 [doi]
- Noxim: An open, extensible and cycle-accurate network on chip simulatorVincenzo Catania, Andrea Mineo, Salvatore Monteleone, Maurizio Palesi, Davide Patti. 162-163 [doi]
- GPU kernels for high-speed 4-bit astrophysical data processingPeter Klages, Kevin Bandura, Nolan Denman, Andre Recnik, Jonathan Sievers, Keith Vanderlinde. 164-165 [doi]
- Loop coarsening in C-based High-Level SynthesisMoritz Schmid, Oliver Reiche, Frank Hannig, Jürgen Teich. 166-173 [doi]
- An interpolation-based approach to multi-parameter performance modeling for heterogeneous systemsDylan Rudolph, Greg Stitt. 174-180 [doi]
- Mixed-length SIMD code generation for VLIW architectures with multiple native vector-widthsErkan Diken, Martin J. O'Riordan, Roel Jordans, Lech Józwiak, Henk Corporaal, David Moloney. 181-188 [doi]
- Comparative analysis of OpenCL vs. HDL with image-processing kernels on Stratix-V FPGAKenneth Hill, Stefan Craciun, Alan D. George, Herman Lam. 189-193 [doi]
- On-demand fault-tolerant loop processing on massively parallel processor arraysAlexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig, Vahid Lari. 194-201 [doi]
- A scheduling and binding heuristic for high-level synthesis of fault-tolerant FPGA applicationsAniruddha Shastri, Greg Stitt, Eduardo Riccio. 202-209 [doi]
- Reconfigurable acceleration of fitness evaluation in trading strategiesAndreea-Ingrid Funie, Paul Grigoras, Pavel Burovskiy, Wayne Luk, Mark Salmon. 210-217 [doi]
- An efficient architecture solution for low-power real-time background subtractionHamed Tabkhi, Majid Sabbagh, Gunar Schirner. 218-225 [doi]
- Large-scale packet classification on FPGAShijie Zhou, Yun R. Qu, Viktor K. Prasanna. 226-233 [doi]
- Efficient implementation of structured long block-length LDPC codesAndrew J. Wong, Saied Hemati, Warren J. Gross. 234-238 [doi]