FastLanes: An FPGA accelerated GPU microarchitecture simulator

Kuan Fang, Yufei Ni, Jiayuan He, Zonghui Li, Shuai Mu, Yangdong Deng. FastLanes: An FPGA accelerated GPU microarchitecture simulator. In 2013 IEEE 31st International Conference on Computer Design, ICCD 2013, Asheville, NC, USA, October 6-9, 2013. pages 241-248, IEEE, 2013. [doi]

@inproceedings{FangNHLMD13,
  title = {FastLanes: An FPGA accelerated GPU microarchitecture simulator},
  author = {Kuan Fang and Yufei Ni and Jiayuan He and Zonghui Li and Shuai Mu and Yangdong Deng},
  year = {2013},
  doi = {10.1109/ICCD.2013.6657049},
  url = {http://dx.doi.org/10.1109/ICCD.2013.6657049},
  researchr = {https://researchr.org/publication/FangNHLMD13},
  cites = {0},
  citedby = {0},
  pages = {241-248},
  booktitle = {2013 IEEE 31st International Conference on Computer Design, ICCD 2013, Asheville, NC, USA, October 6-9, 2013},
  publisher = {IEEE},
}