Physical design for testability for bridges in CMOS circuits

F. Joel Ferguson. Physical design for testability for bridges in CMOS circuits. In 11th IEEE VLSI Test Symposium (VTS'93), 6 Apr 1993-8 Apr 1993, Atlantic City, NJ, USA. pages 290-295, IEEE, 1993. [doi]

@inproceedings{Ferguson93-0,
  title = {Physical design for testability for bridges in CMOS circuits},
  author = {F. Joel Ferguson},
  year = {1993},
  doi = {10.1109/VTEST.1993.313361},
  url = {http://dx.doi.org/10.1109/VTEST.1993.313361},
  researchr = {https://researchr.org/publication/Ferguson93-0},
  cites = {0},
  citedby = {0},
  pages = {290-295},
  booktitle = {11th IEEE VLSI Test Symposium (VTS'93), 6 Apr 1993-8 Apr 1993, Atlantic City, NJ, USA},
  publisher = {IEEE},
  isbn = {0-8186-3830-3},
}