Alexander Finder, Jan-Philipp Witte, Görschwin Fey. Debugging HDL designs based on functional equivalences with high-level specifications. In Lukás Sekanina, Görschwin Fey, Jaan Raik, Snorre Aunet, Richard Ruzicka, editors, 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013. pages 60-65, IEEE Computer Society, 2013. [doi]
@inproceedings{FinderWF13,
title = {Debugging HDL designs based on functional equivalences with high-level specifications},
author = {Alexander Finder and Jan-Philipp Witte and Görschwin Fey},
year = {2013},
doi = {10.1109/DDECS.2013.6549789},
url = {http://doi.ieeecomputersociety.org/10.1109/DDECS.2013.6549789},
researchr = {https://researchr.org/publication/FinderWF13},
cites = {0},
citedby = {0},
pages = {60-65},
booktitle = {16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013},
editor = {Lukás Sekanina and Görschwin Fey and Jaan Raik and Snorre Aunet and Richard Ruzicka},
publisher = {IEEE Computer Society},
isbn = {978-1-4673-6135-4},
}