Edward Flanigan, Rajsekhar Adapa, Hailong Cui, Michael Laisne, Spyros Tragoudas, Tsvetomir Petrov. Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture. In 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India. pages 805-812, IEEE Computer Society, 2007. [doi]
@inproceedings{FlaniganACLTP07,
title = {Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture},
author = {Edward Flanigan and Rajsekhar Adapa and Hailong Cui and Michael Laisne and Spyros Tragoudas and Tsvetomir Petrov},
year = {2007},
doi = {10.1109/VLSID.2007.86},
url = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.86},
tags = {architecture},
researchr = {https://researchr.org/publication/FlaniganACLTP07},
cites = {0},
citedby = {0},
pages = {805-812},
booktitle = {20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India},
publisher = {IEEE Computer Society},
isbn = {0-7695-2502-4},
}