Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits

Bertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin. Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits. In Ricardo Augusto da Luz Reis, Adam Osseiran, Hans-Jörg Pfleiderer, editors, VLSI-SoC: From Systems To Silicon, Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia. Volume 240 of IFIP, pages 55-69, Springer, 2005. [doi]

Abstract

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