Abstract is missing.
- Molecular Electronics - Devices and Circuits TechnologyPaul Franzon, David Nackashi, Christian Amsinck, Neil DiSpigna, Sachin Sonkusale. 1-10 [doi]
- Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment SignalsG. Fraidy Bouesse, Marc Renaudin, Gilles Sicard. 11-24 [doi]
- A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier ArchitecturesLeonardo L. de Oliveira, Cristiano Santos, Daniel Lima Ferrão, Eduardo A. C. da Costa, José C. Monteiro, João Baptista dos Santos Martins, Sergio Bampi, Ricardo Augusto da Luz Reis. 25-39 [doi]
- Defragmentation Algorithms for Partially Reconfigurable HardwareMarkus Koester, Heiko Kalte, Mario Porrmann, Ulrich Rückert. 41-53 [doi]
- Technology Mapping for Area Optimized Quasi Delay Insensitive CircuitsBertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin. 55-69 [doi]
- 3D-SoftChip: A Novel 3D Vertically Integrated Adaptive Computing SystemChul Kim, A. M. Rassau, Stefan Lachowicz, Saeid Nooshabadi, Kamran Eshraghian. 71-86 [doi]
- Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA PlatformsAlberto Donato, Fabrizio Ferrandi, Massimo Redaelli, Marco D. Santambrogio, Donatella Sciuto. 87-109 [doi]
- A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault- Tolerance AnalysisMilos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici. 111-125 [doi]
- Issues in Model Reduction of Power GridsJoão M. S. Silva, L. Miguel Silveira. 127-144 [doi]
- A Traffic Injection Methodology with Support for System-Level SynchronizationShankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen. 145-161 [doi]
- Pareto Points in SRAM Design Using the Sleepy Stack ApproachJun-Cheol Park, Vincent John Mooney III. 163-177 [doi]
- Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCsCésar A. M. Marcon, José Carlos S. Palma, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Ricardo Augusto da Luz Reis. 179-194 [doi]
- Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid PrototypingJerome Quartana, Laurent Fesquet, Marc Renaudin. 195-207 [doi]
- A Novel MicroPhotonic Structure for Optical Header RecognitionMuhsen Aljada, Kamal Alameh, Adam Osseiran, Khalid Al-Begain. 209-219 [doi]
- Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth ConstraintErik Larsson, Stina Edbom. 221-244 [doi]
- On-chip Pseudorandom Testing for Linear and Nonlinear MEMSAchraf Dhayni, Salvador Mir, Libor Rufer, Ahcène Bounceur. 245-266 [doi]
- Scan Cell Reordering for Peak Power Reduction during Scan Test CyclesNabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault. 267-281 [doi]
- On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and CorrectionThilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner. 283-297 [doi]
- Exact BDD Minimization for Path-Related Objective FunctionsRüdiger Ebendt, Rolf Drechsler. 299-315 [doi]
- Current Mask Generation: an Analog Circuit to Thwart DPA AttacksDaniel Mesquita, Jean-Denis Techer, Lionel Torres, Michel Robert, Guy Cathebras, Gilles Sassatelli, Fernando Gehm Moraes. 317-330 [doi]
- A Transistor Placement Technique Using Genetic Algorithm and Analytical ProgrammingCristiano Lazzari, Lorena Anghel, Ricardo Reis. 331-344 [doi]