Evelina Forno, Andrea Acquaviva, Yuki Kobayashi, Enrico Macii, Gianvito Urgese. A Parallel Hardware Architecture For Quantum Annealing Algorithm Acceleration. In IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018. pages 31-36, IEEE, 2018. [doi]
Abstract is missing.