Maximizing area-constrained partial fault tolerance in reconfigurable logic - researchr publication authors

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David L. Foster, Darrin M. Hanna. Maximizing area-constrained partial fault tolerance in reconfigurable logic. In Peter Y. K. Cheung, John Wawrzynek, editors, Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010. pages 259-262, ACM, 2010. [doi]

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