David L. Foster, Darrin M. Hanna. Maximizing area-constrained partial fault tolerance in reconfigurable logic. In Peter Y. K. Cheung, John Wawrzynek, editors, Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010. pages 259-262, ACM, 2010. [doi]
@inproceedings{FosterH10,
title = {Maximizing area-constrained partial fault tolerance in reconfigurable logic},
author = {David L. Foster and Darrin M. Hanna},
year = {2010},
doi = {10.1145/1723112.1723155},
url = {http://doi.acm.org/10.1145/1723112.1723155},
tags = {logic},
researchr = {https://researchr.org/publication/FosterH10},
cites = {0},
citedby = {0},
pages = {259-262},
booktitle = {Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010},
editor = {Peter Y. K. Cheung and John Wawrzynek},
publisher = {ACM},
isbn = {978-1-60558-911-4},
}