Yoshichika Fujioka, Michitaka Kameyama. Configuration memory size reduction of a Dynamically Reconfigurable Processor based on a register-transfer-level packet data transfer scheme. In International SoC Design Conference, ISOCC 2012, Jeju Island, South Korea, November 4-7, 2012. pages 235-238, IEEE, 2012. [doi]
@inproceedings{FujiokaK12,
title = {Configuration memory size reduction of a Dynamically Reconfigurable Processor based on a register-transfer-level packet data transfer scheme},
author = {Yoshichika Fujioka and Michitaka Kameyama},
year = {2012},
doi = {10.1109/ISOCC.2012.6407083},
url = {https://doi.org/10.1109/ISOCC.2012.6407083},
researchr = {https://researchr.org/publication/FujiokaK12},
cites = {0},
citedby = {0},
pages = {235-238},
booktitle = {International SoC Design Conference, ISOCC 2012, Jeju Island, South Korea, November 4-7, 2012},
publisher = {IEEE},
isbn = {978-1-4673-2989-7},
}